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This circuit uses an M-8870 to form a single-ended DTMF receiver. All resistors are 1% tolerance and all capacitors are 5% tolerance. StD (pin 15) is the delayed steering output. It provides a logic high when a received tone pair has been registered and the output latch has been updated. It returns to logic low when the voltage on pin 17 falls below about 2.4 volts. This volage is controlled by the time constant of the 300k resistor and the 0.1uF capacitor. Valid data is presented on Q1 through Q4. Q1 through Q4 can be interpreted as hex data with Q1 the LSB and Q4 the MSB. Therefore a received 1 is presented as 0001, 2 as 0010, ..., 9 as 1001, * as 1010, # as 1100, A as 1101, B as 1110, C as 1111, D as 0000.
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