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Frecuency doubler
This circuit is used to double the frequency of digital clocks. The circuit works by causing a delay, by using gate "a". This delayed clock is the XOR'ed with the original clock and this gives a short pulse at the beginning of the original clock "high" and a second pulse at the start of the original clock "low". The width of these logic high pulses is the number of nanoseconds of the gate delay. More delays may be inserted between gates "a" and "b" for different pulse widths. For CMOS applications, IC1 should be a 4070. For TTL any form of a 74386 ( 74LS386, 74AS386, etc.) should be used. For the 74AS386 the maximum clock-in is about 166 kHz. For a 74LS386 the maximum frequency is about 28 kHz. For a 74386 it is about 25 kHz.